Designing electronics for the military is not simply a matter of choosing rugged enclosures and applying conformal coating. The constraints are architectural, from the system level down to individual transistor selection — and they are fundamentally different from those of consumer or industrial electronics.
This post covers the engineering discipline behind military-grade low-power electronics: how the hardware is structured, which components are permitted, how the printed circuit board is designed, and how power is managed from the platform supply down to the microcontroller’s sleep state.
The Fundamental Architecture: Hierarchical Power Domains
Every credible ultra-low-power military electronics design begins with the same architectural principle: not all subsystems are equal, and most should be off most of the time.
A military sensor node, for example, might operate for 90% of its life in deep sleep — consuming 300 nA from a primary lithium cell — and spend only 0.1% of its time actively transmitting a report. If the designer allows the radio, the processor, and the ADC to share a single always-on power domain, the sleep current is dominated by the radio’s standby consumption (typically 1–10 mA) and the battery lifetime collapses from years to weeks.
The solution is power domain partitioning:
┌─────────────────────────────────────────────────────┐
│ ALWAYS ON (nanowatt domain) │
│ • Wake-up comparator or MEMS sensor front-end │
│ • Real-time clock (RTC) │
│ • Power management IC (PMIC) │
│ Typical current: 100–500 nA │
└────────────────────┬────────────────────────────────┘
│ Hardware interrupt on event
┌────────────────────▼────────────────────────────────┐
│ INTERMITTENTLY ON (microwatt domain) │
│ • Ultra-low-power microcontroller (MCU) │
│ • Sensor acquisition (ADC, I²C/SPI peripherals) │
│ • Local data buffer / flash memory │
│ Typical duration: 10–500 ms per event │
└────────────────────┬────────────────────────────────┘
│ Decision to transmit
┌────────────────────▼────────────────────────────────┐
│ ON DEMAND (milliwatt domain) │
│ • RF transceiver / modem (LoRa, GNSS, cellular) │
│ • Cryptographic accelerator │
│ • High-resolution sensor (camera, radar) │
│ Typical duration: 100–2000 ms per transmission │
└─────────────────────────────────────────────────────┘
Power to each domain is controlled by load switches or DC-DC converters with enable pins. The always-on domain gates the intermittent domain; the intermittent domain gates the on-demand domain. At no point are higher-power subsystems left drawing quiescent current during idle periods.
Component Selection: Military Qualification Tiers
The choice of components is governed by qualification tier. Military procurement contracts specify which tier is acceptable for each application; the designer does not have free choice.
MIL-PRF-38535 qualification tiers
MIL-PRF-38535 (current Revision N, February 2026) is the primary US Department of Defense performance specification for integrated circuits. It defines four qualification classes:
| Class | Description | Temperature Range | Application |
|---|---|---|---|
| Class V / S | Space/flight, hermetic, 100% screening | −55 °C to +125 °C | Space, missile, nuclear |
| Class Q / M | Full military screening, burn-in | −55 °C to +125 °C | Airborne, naval, critical ground |
| Class B | High-reliability, lot acceptance testing | −55 °C to +125 °C | General military |
| Class G | COTS with additional screening | −40 °C to +85 °C | Non-critical military, COTS-based programmes |
For unattended ground sensors and tactical IoT nodes — where cost and lead time matter but reliability is critical — Class G (COTS with screening) is typically specified. Class G parts undergo additional burn-in, electrical characterisation, and lot acceptance testing (LAT) beyond the commercial baseline, providing significantly higher confidence in field reliability without the cost and lead time of full military screening.
Ultra-low-power MCU selection
The microcontroller is the heart of a low-power military node. Key selection criteria for military use:
Power states: Military MCUs must offer a hierarchy of low-power modes — run, sleep, deep sleep, hibernate/standby, and shutdown — with deterministic wake-up times and complete peripheral state retention across all modes.
Leading platforms for military and defence-adjacent low-power applications:
| MCU Family | Sleep Current | Wake-up Time | Key Feature |
|---|---|---|---|
| STM32L5 (ST) | 300 nA | 5 µs | Arm TrustZone, hardware crypto |
| STM32WL (ST) | 1.08 µA | 5 µs | Integrated LoRa SoC, first of its kind |
| MSP430 FR (TI) | 400 nA | 3.5 µs | FRAM non-volatile memory, ultra-low FRAM write power |
| SAML21 (Microchip) | 200 nA | 8 µs | Event System for peripheralless wake-up |
| nRF9160 (Nordic) | 2.5 µA (LTE-M idle) | 1 ms | Integrated LTE-M/NB-IoT modem |
| EFM32PG (Silicon Labs) | 75 nA | 2 µs | Industry-leading sleep current |
The STM32WL is of particular interest for military LoRa applications: it is the world’s first System-on-Chip to integrate an Arm Cortex-M4 application processor with a sub-GHz LoRa-capable radio in a single die, eliminating the inter-chip power overhead of a separate radio module.
External nano-timer technique: For applications where even the MCU’s deep-sleep current is too high, the TPL5110 nano-timer IC from Texas Instruments can be used to cut power to the MCU entirely between measurement events. The nano-timer draws only 35 nA in its own standby state, waking the MCU at a configured interval, then cutting power again after the MCU asserts a “done” signal. This reduces the system standby current from the MCU’s typical 300–2,000 nA to the nano-timer’s 35 nA — a 10× to 50× improvement.
Power Supply Engineering for Military Platforms
The power supply is not just a voltage converter. In military systems, it is the first line of protection against the electrical environment of the platform.
Platform voltage standards
| Platform | Voltage | Standard |
|---|---|---|
| Ground vehicles (NATO) | 28V DC | MIL-STD-1275E |
| Ground vehicles (NATO, 42V future) | 42V DC | STANAG 4193 |
| Fixed-wing aircraft | 28V DC / 115V AC / 270V DC | MIL-STD-704F |
| Rotary-wing aircraft | 28V DC | MIL-STD-704F |
| Naval vessels | 24V DC / 440V AC | MIL-STD-1399 |
Transient protection requirements
Military vehicle buses are electrically violent. MIL-STD-1275E specifies that 28V DC vehicle bus electronics must survive:
– Steady-state voltage: 16–32V DC
– Load dump transient: up to +100V for 500 ms
– Cold-crank transient: voltage dip to 9V for up to 100 ms
– Inductive spikes: up to ±600V peak (60 µs duration)
A low-power sensor payload drawing 10 mA from the vehicle bus must therefore be protected by:
1. A transient voltage suppressor (TVS) diode or transient protection module at the input
2. A wide-input-range DC-DC converter (e.g., 9–36V input to 3.3V output) with >90% efficiency across the input range
3. EMI input filtering (common-mode choke + capacitors) to meet MIL-STD-461G conducted emission limits
DC-DC converter efficiency
In a battery-powered node, converter efficiency is not a convenience metric — it is a battery lifetime multiplier. A 10% improvement in converter efficiency delivers approximately 10% more capacity from the same cell. Military low-power designs specify converters with:
– >90% peak efficiency at the nominal load point
– >80% efficiency across the full load range (important because light-load efficiency often collapses in cheap converters)
– Low quiescent current (< 10 µA) in standby / burst mode
PCB Design Practices for Military Low-Power Systems
The printed circuit board is where system architecture meets physical reality. Military low-power PCBs incorporate design disciplines that are unnecessary or optional in commercial work but mandatory in this context.
Layer stack and ground plane strategy
Military low-power PCBs use a minimum of 4 copper layers:
– Layer 1: Component side — signal routing, component placement
– Layer 2: Continuous ground plane — provides return path for all signals, reduces radiated emissions (MIL-STD-461 RE102 compliance)
– Layer 3: Power plane — filtered supply rails, isolated power domains
– Layer 4: Signal / secondary components
The continuous ground plane on Layer 2 is non-negotiable for MIL-STD-461 compliance. Slotted or split ground planes introduce impedance discontinuities that radiate.
Guard rings for sub-microampere leakage control
In a system where the target sleep current is 300 nA, a PCB surface leakage current of 1 µA — easily achievable on a humid, contaminated surface — will dominate the power budget and destroy the design specification.
Guard rings are grounded copper traces or pours placed around the high-impedance inputs of sensitive components (ADC inputs, MCU analog pins, battery positive rail) to intercept surface leakage before it reaches the sensitive node. Guard rings are connected to a driven shield potential — typically the same voltage as the guarded node — to actively cancel leakage, not just intercept it.
Component placement for thermal management
Military electronics must operate across the full military temperature range: −40 °C (Class G) to +85 °C, or −55 °C to +125 °C (full military). Thermal design includes:
– High-dissipation components (DC-DC converters, power transistors) placed near the enclosure wall for direct thermal conduction to the heat-spreading case
– Thermal vias under high-power components, connecting the component pad through the PCB to a ground plane that spreads heat
– Temperature-sensitive components (crystal oscillators, precision references) placed away from heat sources and, where possible, thermally compensated in firmware
Solder and finish selection
Commercial electronics increasingly use tin-based lead-free solder, but tin whiskers — crystalline tin growths that can bridge PCB conductors and cause shorts — are a known long-term reliability failure mode. Tin whiskers have caused failures in satellites and military systems after multi-year storage or operation.
Military programmes mitigate this by:
– Specifying tin-lead (SnPb) solder where exempted from RoHS under EU defence exclusions, or
– Specifying matte tin (Sn) with a minimum tin thickness and elevated-temperature burn-in to stabilise the tin microstructure, or
– Specifying alternative finishes (NiPdAu, ENIG) for component leads and PCB surface finish
Decoupling strategy
Every power pin on every active component receives a decoupling capacitor. Military low-power designs implement a three-tier strategy:
– Bulk decoupling (10–100 µF electrolytic or ceramic): at every major power entry point, absorbs load steps during mode transitions
– Mid-frequency decoupling (100 nF ceramic, X7R): at every IC power pin, filters 1–100 MHz switching noise
– High-frequency decoupling (10 nF C0G/NP0 ceramic): for RF and high-speed digital supply pins, filters GHz-range noise that would violate MIL-STD-461 RE102 radiated emission limits
Firmware Architecture for Low-Power Operation
Hardware alone cannot deliver ultra-low power. The firmware must be designed around power as a first-class constraint.
Event-driven programming model
Military low-power firmware avoids polling loops entirely. All state transitions are triggered by hardware interrupts:
– Timer interrupt from the RTC: wake up, acquire a sensor reading, buffer it
– Hardware comparator interrupt: detection event — wake up, classify, decide whether to transmit
– DMA transfer complete interrupt: radio transmission finished — disable radio, return to deep sleep
Between interrupt handlers, the firmware calls __WFI() (Wait For Interrupt) or equivalent, placing the MCU in its lowest-power mode until the next event.
Data buffering and store-and-forward
Transmitting every sensor reading individually is inefficient — the radio wake-up energy overhead dominates. Military low-power firmware buffers multiple readings in local flash or FRAM memory and transmits them as a single aggregated payload. ThingsLog’s LPMDL-1105, for example, buffers 96 sensor readings (24 hours at 15-minute intervals) and transmits once per day during a scheduled communication window — the same architecture validated in the Antarctic deployment described in Case Study 3.
Adaptive duty cycling
Advanced implementations adjust the sleep interval dynamically based on detected threat level, battery state, or network congestion. In high-priority states (active detection event), the node transmits more frequently. In background monitoring, it stretches the sleep interval to maximise battery life. This mirrors the adaptive duty cycling research being pursued in the IoBT programme.
Series Navigation
- Post 1: Why Low Power Matters in Military Operations
- Post 2: Key Application Domains
- [You are here] Post 3: How Military Low-Power Electronics Are Built
- Post 4: Protective Coatings for Military Electronics
- Post 5: Military Electronics Standards
- Post 6: IP Ratings and Ingress Protection
- Case Study 1: DARPA N-ZERO
- Case Study 2: LoRa Tactical Troop Tracking
- Case Study 3: ThingsLog LPMDL in Antarctica
- Case Study 4: Army CombatConnect
